The code tracking operations are performed by a Synchronisation Unit. Several types of code tracking loops have been extensively applied in practical applications and the most popular solution is the so-called Early-Late synchronizer.
The Synchronisation Unit receives, as input, the baseband signal y(t) from the receiver front-end, oversampled at the frequency fs=N·FC and with at least two samples per chip (N≧2), and feeds a finger of the Rake receiver with one sample per chip (i.e. the optimal sample), as shown in FIG. 1. Each finger of the Rake receiver requires its own Synchronisation Unit because the values of timing offset of the different multi-path components demodulated by the different fingers of the Rake receiver are usually not the same.
The fine timing synchronisation can be achieved by performing some kind of interpolation among the received samples, in order to get the exact value or, at least, to approximate the received signal in correspondence of the optimal sampling instants topt. This technique is well known and is disclosed for example in F. M. Gardner, “Interpolation in digital modems—Part I: Fundamentals”. IEEE Trans. Communications vol. 41, pp. 502-508, March 1993 or in L. Erup, F. M. Gardner, “Interpolation in digital modems—Part II: Implementation and Performance”. 
The optimal sampling instant topt(t) varies with time due time variant nature of the wireless channel and corresponds to the instant in which the amplitude of the received signal is maximal and, simultaneously, the Inter-Symbol Interference (ISI) is minimal. By sampling the received signal in correspondence of the optimal sampling time, it is possible to maximise the Signal to Noise Ratio (SNR) and therefore minimise the Bit Error Rate (BER) at the output of the receiver. The optimal sampling time can be observed in the eye diagram as the point of maximum opening, as shown in FIG. 2.
In the following it is described the principle of a Synchronisation Unit based on the known art. The description is based on the case of a real signal y(t), but the extension to a complex signal y(t) is straightforward.
The block diagram of a Synchronisation Unit 1, described in the prior art is, shown in FIG. 3. The considered scheme operates with a feedback loop. A time continuous signal y(t) is received at the input of the Analog to Digital Converter 2. The signal y(t) is a sequence of pulses with period TC and shaped, for example, by a couple of root raised cosine (RRC) filters
      y    ⁡          (      t      )        =            ∑              k        =        0            ∞        ⁢                  u        k            ·              h        ⁡                  (                      t            -                          k              ·                              T                C                                              )                    where uk={−1,+1} is the sequence of transmitted chips and h(t) is the impulse response of the equivalent Raised Cosine (RC) filter with the following expression
      h    ⁡          (      t      )        =                    sin        ⁡                  (                                    π              ·              t                                      T              C                                )                                      π          ·          t                          T          C                      ·                  cos        ⁡                  (                      α            ·                                          π                ·                t                                            T                C                                              )                            1        -                              (                          2              ·              α              ·                              t                                  T                  C                                                      )                    2                    The unilateral bandwidth of the signal y(t) is equal to
  B  =            (              1        +        α            )              2      ·              T        C            where α is the roll-off of the RRC shaping filters.
The ADC converter 2 takes samples of y(t) at uniform intervals ts, which correspond to an ADC sampling frequency of fs=1/ts. The sampling of the analog baseband signal can be performed with different sampling rates. However, the Nyquist criterion requires a minimum ADC sampling rate of two times the unilateral signal bandwidth, namely fs≧2·B.
The signal samples y(n·ts)=y(n) at the output of the ADC converter 2 are provided to the interpolator 4 that computes the interpolated values yl(m·tl)=yl(m) at intervals tl. The goal of the interpolator is to increase the time resolution after the ADC conversion, so that the time spacing tl of the samples at the output of the interpolator is smaller that the time spacing ts of the samples at the output of the ADC. In general we have
            t      g              t      1        =  Kwhere K is an integer number greater than one.
Being the samples y(n) at the output of the ADC not taken in correspondence of the optimal time instant, the Synchronisation Unit must first estimate the optimal sampling instant {circumflex over (t)}opt and then compute or approximate the value of y(t) in correspondence of that instant. The value y({circumflex over (t)}opt) is then provided at the output of the Synchronisation Unit for the subsequent signal processing.
The principle of timing synchronisation through digital interpolation is shown in FIG. 4 for a case of linear interpolation with K=4.
In the example of FIG. 4 the signal y(t) in correspondence of the optimal sampling instant topt is approximated with the interpolated value yI(m+3).
The interpolated value yl(m+3) is calculated as follows: first it is computed the middle point yl(m+2) between two consecutive samples y(n) and y(n+1) at the output of the ADC
            y      I        ⁡          (              m        +        2            )        =                    y        ⁡                  (          n          )                    +              y        ⁡                  (                      n            +            1                    )                      2  
Similarly, the other two interpolated values yl(m+1) and yl(m+3) are computed as the average between one ADC sample and the interpolated value yl(m+2) calculated in the previous step
                    y        I            ⁡              (                  m          +          1                )              =                                        y            ⁡                          (              n              )                                +                                    y              I                        ⁡                          (                              m                +                2                            )                                      2            =                                    3            ·                          y              ⁡                              (                n                )                                              +                      y            ⁡                          (                              n                +                1                            )                                      4                                y        I            ⁡              (                  m          +          3                )              =                                        y            ⁡                          (                              m                +                2                            )                                +                                    y              I                        ⁡                          (                              n                +                1                            )                                      2            =                                    y            ⁡                          (              n              )                                +                      3            ·                          y              ⁡                              (                                  n                  +                  1                                )                                                    4            Of course, by using a more complex interpolation schemie (e.g. parabolic, cubic) or increasing the resolution of the interpolator (i.e. increasing K) it is possible to make more precise the estimate of the received signal in correspondence of the optimal sampling instant.
The synchronization unit of FIG. 3 also includes other elements that are essential for the synchronization process. A data filter 5 processes the interpolated samples and selects the optimal sample for the subsequent signal processing. The data filter is indicated within the feedback loop, but it can also be placed outside of the loop. Post-placement may be advantageous in terms of complexity when the data filter is more complicate than the interpolator and a relatively high sampling rate is employed for interpolation.
The optimal sampling instant topt is estimated by a timing error detector block 6 and filtered by a loop filter 7. The goal of the loop filter is to reject the effect of noise that may affect the optimal sampling time estimate. Finally, the loop filter output drives a controller 3, which provides the control signal to the interpolator 4.
Starting from the general structure of a Synchronisation Unit, shown in FIG. 3, it is possible to analyse its application in the particular case of a digital CDMA receiver.
A known solution for performing the code tracking operations in a CDMA receiver is the so-called Early-Late synchronizer disclosed for example in John G. Proakis, “Digital Communications”, 3rd edition, Mc Graw-Hill, New York, 1995.
The joint application of the interpolation and the Early-Late concept for the synchronisation of a CDMA receiver can be found in R. De Gaudenzi, M. Luise, “A Digital Chip Tuning Recovery Loop for Band-limited Direct-Sequence Spread-Spectrum Signals”. IEEE Trans. On Communications, vol. 41, No. 11, November 1993.
An Early-Late synchronizer exploits the symmetry properties of the signal autocorrelation at the output of the receiver-matched filter.
In the following we suppose that the signal at the input of the Early-Late synchronizer is sampled with two samples per chip (N=2). Two subsequent samples at the input of the Early-Late synchronizer are then separated in time by TC/2 (with TC=1/FC=chip period).
In order to introduce a suitable mathematical notation for sequences with different rates, we denote with k the discrete time index related to the chip period so that e(k)=e(k·TC). We also denote with SF the spreading factor. The period of the information symbols before the spreading process is equal to TS=SF·TC and the discrete time index related to this symbol period is equal to (k div SF), where A div B is the integer part of the quotient between A and B.
Each received chip can be characterised by an early, a middle and a late samples defined as follows:
early sample: is the sample that anticipates the optimal sampling time instant. The early sample is denoted with eI(k) and eQ(k) for the in-phase and in-quadrature component respectively;
middle sample: is the sample that, in the absence of timing errors, corresponds to the optimal sample or equivalently to the peak of the received impulse h(t). The middle sample is denoted with mI(k) and mQ(k) for the in-phase and in-quadrature component respectively;
late sample: is the sample that is delayed with respect to the optimal sampling time instant. The late sample is denoted with lI(k) and lQ(k) for the in-phase and in-quadrature component respectively. The late sample of a given chip is also the early sample of the next chip.
The definition of early, middle and late samples is clarified in FIG. 5 for the in-phase component and in the case of perfect timing synchronisation. From FIG. 5 it is possible to notice that the middle sample is the one with the higher energy and minimum ISL Consequently, it has to be provided to the Rake finger for the descrambling and despreading operations.
Moreover, from FIG. 5 it is possible to observe that, if the impulse response of the complete system is symmetrical and the system has achieved a perfect timing synchronisation, then the energies of the early and late samples are identical.
The two conditions of perfect timing synchronisation can be expressed as follows:
Perfect timing synchronisation  εm=mI2(k)+mQ2(k)=maximum
Perfect timing synchronisation  εe=eI2(k)+eQ2(k)=εI=lI2(k)+lQ2(k)
where εe, εm, εl are the energies of the early, middle and late samples respectively.
In the presence of noise the identification of the sample with maximum energy is usually difficult. Instead of sampling the signal in correspondence of the peak, the Early-Late synchronizer identifies the optimal sampling instant through the second condition: the energy of the early and late samples has to be equal or, in other words, the difference between the two energies must be reduced to zero (εe−εl=0). When such condition is fulfilled the sample between early and late (i.e. the middle) is the optimal sample to be provided to the Rake finger.
Taking into account that in a CDMA system the signal to noise ratio on the channel is very low, the condition εe−εl=0 must be verified on the symbols after the operations of despreading and integration. Averaging over SF samples leads to mean values of the early and late sample energies and reduces the energy fluctuations due to noise and interference from other users.
A simplified block diagram of a prior art Early-Late synchronizer is shown in FIG. 6 for the general case of a real PN (Pseudo Noise) code ce(k). However, the same scheme is valid in case of complex PN code by simply replacing each couple of real multiplication units with one complex multiplication unit.
The Early-Late synchronizer of FIG. 6 uses two correlators: the first performs the despreading and integrate and dump operations on the early samples while the second correlator performs the same operations on the late samples. The outputs of the two correlators are then squared in order to get the energy of the despreaded symbols, to remove the modulation of the data sequence and the phase rotation introduced by the propagation channel. Finally, an error signal ξ is computed by taking the difference of the two-correlator outputs.
After the operations of despreading, integration, squaring and sum of the in-phase and in-quadrature components the error signal, for a certain timing error τ=t−topt, is given byξ(kdivSF)=E(kdivSF)−L(kdivSF)
The characteristic of the Early-Late synchronizer in terms of error signal ξ as a function of the timing error τ is shown in FIG. 7. The Early-Late characteristic, due to its particular shape, is usually referred to as S-curve.
From FIG. 7 we observe that when a timing offset is present (τ≠0), the error signal ξ at the output of the Early-Late synchronizer is nonzero and the time position of the early, middle and late samples must be delayed or advanced (depending on the sign of the error) to get the optimal sampling instant.
An alternative solution for finely adjusting the time position of the early, middle and late samples, without delaying or advancing their positions, consists in using three digital interpolators as shown, in the particular case of a timing offset τ=TC/4, in FIGS. 8 and 9.
Two of these interpolators are used to compute the early B and the late L samples while the-third interpolator is used to compute the middle M sample (i.e. the optimal sample with the maximum energy). The early and late samples are provided to the correlators for the computation of the error signal ξ, while the middle sample is provided to the Rake finger for the subsequent signal processing (descrambling, despreading, channel estimation and compensation, decoding, etc.).
If we consider in FIG. 8 the early E, the middle M and the late L samples, we observe that, by means of a linear interpolator, it is possible to generate, with a certain resolution, all the samples between two subsequent values early E and middle M or middle M and late L In the case of error signal larger than zero the optimal sampling time is delayed with respect to the middle M sample and therefore the value of the optimal sample can be computed with a linear interpolation between the middle M and the late L samples. In a similar way for an error signal lower than zero, the optimal sample is computed by means of a linear interpolation between the early E and the middle M samples.
In order to compute the delayed or advanced version of the samples early E and late L, determining the error signal, it can be necessary to interpolate the early E sample between the previous sample E−1 and the middle M sample and, in similar way, the late L sample between the subsequent sample L+1 and the middle M sample, as it is possible to observe in FIG. 9. Therefore a Synchronisation Unit based on the Early-Late synchronizer requires the knowledge of five subsequent samples E−1, E, M, L, L+1 of the incoming signal spaced of TC/2 among each other.
The three interpolators are used to finely adjust the time position of the early, late and middle samples feeding the correlators and the Rake finger respectively. These interpolators are controlled by a digital signal derived from the error signal ξ of the Early-Late synchronizer. If the loop is correctly designed so to obtain a negative feedback, the system automatically minimizes the error signal by converging towards the error zero condition. The minimum error condition is equivalent to say that the middle sample is the one with the maximum energy and therefore the optimal one.
The time position of the three interpolated samples (early, middle and late) is moved backward or forward by a time factor δ when the error signal is respectively positive or negative. The factor δ represents the time resolution of the interpolators and it is usually equal to TC/8.
The Early-Late synchronizer is a closed loop system that reaches a steady state when the error signal is exactly zero. In practice, because of the finite arithmetic precision of the device, the error signal varies around the zero value by alternating negative and positive values.
Consequently the control signals of the interpolates, which are derived from the sign of the error signal ξ, oscillate around the steady state values. Such behaviour allows a continuous tracking of the optimal timing but, at the same time, introduces an undesired jitter on the time-position of the middle sample.
The timing jitter introduces a performance degradation in the whole system. A known solution for compensating such performance degradation is to increase the time resolution of the interpolators. Nevertheless such solution is rather expensive, the complexity of a digital interpolator is generally proportional to its resolution, because of the mathematical operations required to perform interpolation.
The complexity of the single interpolator affects negatively the chip area, especially in case of a base station receiver where many of these interpolators are required to process the signals of the various users. Each Rake finger of a base station needs six interpolators: early, middle and late for both signal components (I and Q). Moreover if we consider, as a possible example, a UMTS base station with 64 different Rake receivers, each with Nf=8 fingers, it is then evident from these numbers that employing interpolators having reduced complexity is a remarkable advantage.
The Applicant has tackled the problem of reducing the timing jitter of the middle interpolator, without increasing the time resolution of the corresponding digital interpolator.
The Applicant observes that, alternating between negative and positive values of the error signal around the zero value, although allowing a continuous tracking of the optimal timing, does not give any positive contribution to the synchronization process. On the contrary, such behaviour introduces a timing jitter on the position of the middle sample which influences negatively the whole system performance.
In view of the above, it is an object of the invention to provide an early-late synchronizer having a reduced timing jitter. Thanks to the reduced timing jitter, it is possible to reduce the resolution of the interpolators and, consequently, the area of the silicon chip in which the system is integrated.
The above and other objects are reached by the method and the device realised according to the invention, as claimed in the accompanying claims.